Suppressing Simultaneous Switching Noise Using Electromagnetic Bandgap (EBG) Structures

1. SSN Mechanism & EBG Principle

• SSN Generation:
  $V_{noise}=L_{loop}\cdot N\cdot \frac{dI}{dt}$

  • $L_{loop}$: P/G loop inductance (0.5-2nH)

  • $N$: Simultaneously Switching gates

  • $dI\mathrm{/}dt$: Current slew rate (up to 1A/ns)

• EBG Bandgap Property:

  Frequency	Attenuation Mechanism	Suppression
  In-band (e.g., 1-5GHz)	Propagation prohibition	>40dB
  Out-of-band	Partial reflection/absorption	<10dB

2. EBG Topologies & Design

2.1 Topology Comparison

2.2 Key Design Formulas

• Center Frequency:
  $f_c=\frac{c}{2a\sqrt{{\epsilon }_{eff}}}(a\text{: unit period})$
  

• Bandwidth:
  $BW=\frac{1}{\pi \sqrt{L_{eq}{C}_{eq}}}(L_{eq}\text{: equiv. inductance},C_{eq}\text{: equiv. capacitance})$
  

3. Design Optimization Flow

3.1 Parameter Tuning

4. PCB Implementation

5. Performance Validation

5.1 Simulation

5.2 Measurement

6. Design Constraints & Solutions

7. Application Cases

• 5G Baseband FPGA:

  • Issue: DDR4 3200MHz SN-induced BER

  • Solution: 5×8 mushroom EBG in P/G layer (a=3mm)

  • Result: 32dB noise reduction @1.8-3.2GHz, BER

• AI Accelerator Card:

  • Issue: GPU SSN coupling to PCIe

  • Solution: Local EBG island (3×3 units, f_c=4.5GHz)

  • Result: PCIe 4.0 eye opening ↑40%