Seed Layer Selective Etching Control in mSAP Manufacturing

2025-05-06

Introduction

The modified Semi-Additive Process (mSAP), critical for HDI PCB fabrication, achieves 5/5μm line/space through ultrathin seed layer plating and selective etching. Uniformity and selectivity in seed layer etching directly determine line wall profiles, suRFace roughness, and impedance consistency.

1. Seed Layer Materials and Etching Mechanisms

1.1 Typical Seed Layer Structure (Figure 1)

mSAP uses bilayer stacks:

Barrier layer: 10-20nm Ti/TiN to prevent copper diffusion;
Conductive layer: 100-200nm Cu for electroplating.

1.2 Selective Etching Chemistry

Two-step etching:

Cu etchant: H₂SO₄-H₂O₂ system with >100:1 selectivity (Cu vs. Ti):
$Cu + H_{2} O_{2} + H_{2} S O_{4} \to C u S O_{4} + 2 H_{2} O$
Ti etchant: HF-HNO3 mixture with >500:1 selectivity (Ti vs. Cu):
$Ti + 4 H N O_{3} + 6 H F \to H_{2} T i F_{6} + 4 N O_{2} ↑ + 4 H_{2} O$

2. Key Process Parameters

2.1 Copper Etching Control

Concentration management:
- Maintain 8-12wt% H₂O₂ to prevent Cu+ accumulation;
- Temperature control at 30±2℃ (25% rate increase per 5℃ rise);
Flow design:
- Fan nozzles with 0.15-0.25MPa pressure ensure ≤±5% film uniformity.

2.2 Titanium Residue Prevention

Endpoint detection:
- In-situ EIS monitors Ti layer resistance (±1nm accuracy);
Post-clean:
- DIW + 40kHz ultrasonic cleaning removes H2TiF6 residues.

3. Defect Analysis and Solutions

3.1 Undercut Suppression

Issue: Excessive lateral etching (>0.3μm);
Solutions:
- Add 0.5-1.0g/L benzotriazole (BTA) as inhibitor;
- Reduce flow velocity to 0.8m/s to minimize turbulence.

3.2 Seed Layer Residue Control

Issue: Incomplete Ti etching causing shorts;
Solutions:
- Increase agitation (500-600rpm) for better mass transfer;
- Plasma ashing pre-treatment removes carbonized photoresist.

4. Equipment and Monitoring

4.1 Vertical Continuous Processing (VCP) Tool

Multi-chamber design: Cu etch → rinse → Ti etch → rinse → dry (cycle time ≤3min);
Auto-dosing: ORP sensors regulate H2O2 concentration (±0.5% variation).

4.2 In-line Metrology

Optical interferometer: Measures seed layer thickness (±2nm);
XRF spectrometer: Detects metal residues (<10ppm detection limit).

5. Case Study: IC Substrate Parameters

Cu seed layer: 150nm;
Etch uniformity: Within-wafer (WIW) ≤3%, wafer-to-wafer (WTW) ≤5%;
Line sidewall angle: 88±2° (target 90°);
Impedance control: ±5% deviation at 10GHz.