Preventing Sidewall Serration in Low-Profile Copper (HVLP) Etching

Hyper Very Low Profile (HVLP) copper foil (Rz<3μm) is critICal for high-frequency PCBs, where etching quality directly impacts signal integrity. Sidewall serration—periodic edge roughness (>0.5μm)—causes additional 0.2dB/cm loss at mmWave frequencies.
1. Serration Formation Mechanisms
1.1 Micro-Etching Dynamics (Figure 1)
Copper etching anisotropy:
Cu+2FeCl3→CuCl2+2FeCl2
Serration arises from competing processes:
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Vertical etching: Grain boundary preferential dissolution;
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Lateral undercut: Chemical seepage at resist edges.
1.2 Critical Factors
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Resist slope angle: <70° increases undercut risk by 30%;
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SuRFace tension: >40mN/m causes non-uniform wetting;
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Crystal orientation: <100> etches 1.8x faster than <111>.
2. Etchant Formulation Optimization
2.1 Advanced Chemistry
| Component | Concentration | Function |
|---|---|---|
| FeCl₃ | 2.0-2.5mol/L | Main oxidizer |
| H₂SO₄ | 0.5-1.0mol/L | Stabilizes Fe³+ |
| PEG-600 | 0.3-0.5g/L | Reduces surface tension |
| Benzoimidazole (BIA) | 0.1-0.2g/L | Grain boundary inhibitor |
| Alkyl sulfonate | 0.05-0.1g/L | Wetting agent |
2.2 Parameter Monitoring
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Specific gravity: 1.32±0.02g/cm³ (refractometry);
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ORP: 450-500mV (vs. Ag/AgCl);
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Fe²+: <0.15mol/L (electrolytic regeneration if exceeded).
3. Process Parameter Tuning
3.1 Spray & Transport
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Pressure: 0.8-1.2bar (high pressure damages resist);
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Nozzle angle: 15° tilt for laminar flow (turbulence <5%);
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Speed: 1.2-1.5m/min (etch factor 2.5-3.0).
3.2 Temperature & Time
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Temperature: 50±1℃ (>2℃ fluctuation triggers orientation-selective etching);
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Multi-stage etching:
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Pre-etch: 30s for oxide removal;
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Main etch: 90s for vertical profile;
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Finishing: 20s with PEG for sidewall smoothing.
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4. Equipment Engineering
4.1 Spray Chamber Design
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Zoned flow: Independent upper/lower nozzles to compensate gravity effects;
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Vortex suppressor: Honeycomb baffles reduce Reynolds number <2000.
4.2 Resist Lamination
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Vacuum chuck: Porous ceramic (10μm pores), -60kPa pressure;
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Pre-bake: 75℃×5min to eliminate resist-copper gaps (<0.1μm).
5. Defect Inspection & Validation
5.1 Sidewall Characterization
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Laser confocal microscopy: 3D profile analysis of serration period/amplitude (Figure 2);
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SEM: Grain boundary inspection to evaluate BIA performance.
5.2 Electrical Testing
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Impedance consistency: ±1.5% intra-board variation (10GHz);
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Insertion loss: 0.18dB/cm reduction at 28GHz.
6. Case Studies & Data
6.1 77GHz Automotive Radar
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Copper: HVLP Rz=2.1μm;
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Parameters:
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Etchant: FeCl₃ 2.3mol/L + PEG-600 0.4g/L;
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Spray: 1.0bar, 52℃;
-
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Results:
Metric Before After Serration (μm) 0.72 0.15 Impedance error ±3.8% ±1.2% Etch factor 1.8 3.1
6.2 Reliability Tests
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Thermal shock: -40℃~125℃, 500 cycles (no micro-cracks);
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Humidity aging: 85℃/85%RH, 1000h (<0.5% impedance drift).

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