PCB Via Size and Trace Width Matching Design Guide

Abstract: The matching between via size and trace width critICally impacts signal integrity, manufacturability, and reliability. Per IPC-2221, core principles are "via current capacity ≥ trace current capacity" and "impedance continuity", with specific rules detailed below.

1. Basic Dimension Definitions

Note:

• Current Formula: I (Amps), k=0.048 (outer)/0.024 (inner), ΔT=temp rise (°C);

• Aspect Ratio (board thickness/hole dia) ≤10:1 (ensures Cu plating ≥18μm).

2. Matching Rules

1. Current Capacity Matching:

   • Via Current: I_via ≈ 0.8×D (D in mm, I in A)
     *e.g., D=0.3mm → I_via≈0.24A*

   • Trace Current: W (mm) = I / (0.048×ΔT⁰·⁴⁴)
     *e.g., I=0.5A, ΔT=10°C → W≈0.25mm*

   • Requirement: I_via ≥ I_trace → D ≥ 1.25×W

2. Impedance Continuity Matching:

   • Via impedance tolerance ≤±10% (high-speed):

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     Z_{via} ≈ \frac{87}{\sqrt{\varepsilon_r+1.41}}\ln\left(\frac{5.98H}{0.8D}\right)  (Ω)  

     (H: via stub length, ε_r: Dk)

   • Design Examples:

     • When W=0.2mm (50Ω microstrip), use D=0.25mm (Z_via≈45–55Ω);

     • Differential vias: Paired via spacing S=2W to minimize discontinuity.

3. Application-Specific Standards

Failure Limits:

• Drill breakage ↑30% if D<0.2mm;

• Thermal cracking risk ↑50% if P<D+0.15mm.

4. DFM Rules

1. Via-to-Trace Spacing:

   • Edge-to-edge distance ≥0.15mm (prevent copper tear);

   • Center spacing ≥3D between via groups (avoid drill drift).

2. Trace-to-Pad Connection:

   • Exit trace from pad center (angle ≤45°);

   • Add teardrops (width taper ratio 0.6).

5. Verification & SIMulation

1. Current Simulation:

   • Use IPC-2152 calculator or HyperLynx PI to verify ΔT<20°C;

2. Impedance Simulation:

   • Model via in HFSS, ensure return loss <-25dB up to 10GHz;

3. Process Validation:

   • Cross-section for Cu thickness (Class 3 ≥18μm);

   • Thermal cycling (-55°C~125°C, 1000 cycles) without fracture.

Conclusion

Via-trace matching follows "electrical priority, process safeguard":

• General Rule: D ≥ 1.25×W (current), P = D + 0.2–0.3mm (manufacturing);

• High-Speed: Via impedance tolerance ≤±10%, diff-pair via spacing S=2W;

• HDI Solution: Laser microvias (D=0.1mm) with ultra-fine traces (W=0.08mm).
  Design Redlines:

1. Never use unfilled vias in BGA pads (Via-in-Pad requires plating fill);

2. For insufficient current, add parallel vias (do not enlarge single via).