Mitigating Inter-Symbol Interference (ISI) in Ultra-High-Speed PCB Designs (112Gbps+)

I. ISI Mechanism & QuantifICation

1. Loss-Dominated Formula
   $IS{I}_{pp}=K\cdot e^{-\alpha L}\cdot \sqrt{\frac{B}{f_0}}$

   • $\alpha$: Loss per unit length (dB/inch)

   • $L$: Trace length

   • $B$: Baud rate (56GBaud for PAM4 @112Gbps)

2. Key Impact Factors

   Factor	ISI Contribution	Control Target
   Dielectric Loss (Df)	45%	Df≤0.001 @10GHz
   Skin Effect Roughness	30%	Ra≤0.3μm (HVLP Cu)
   Impedance Discontinuity	15%	ΔZ≤±3Ω
   Reflection Noise	10%	Return Loss<-20dB

II. Material & Stackup Optimization

1. Substrate Selection

   Material	Df@10GHz	Data Rate	Cost Factor
   Megtron 7	0.001	≤112Gbps	1.8x
   Rogers Kappa 438	0.002	56-112Gbps	1.3x
   Standard FR4	0.025	≤28Gbps	1.0x

2. Stackup Example (12-Layer)

   L1: Signal (short traces)    ↓ Prepreg: 2mil Ultra-Loss (Df=0.001)    L2: Solid Ground Plane  ← Critical!    ↓ Core: 3mil Megtron 7    L3: Signal (112G diff pairs)    ↓ Prepreg: 2.5mil    L4: Power Plane (split zone with cap arrays)  

   Rules:

   • High-speed layer-to-ground distance ≤4mil

   • Orthogonal routing on adjacent layers (angle≥75°)

III. Critical Routing Techniques

1. Impedance & Loss Control

   • Diff Pair Specs:

     Width/Spacing(mil)	Impedance(Ω)	Loss(dB/inch@28GHz)
     5/5	85±2	0.65
     4/6	100±1	0.58

   • Back-Drilling:
     $L_{stub}<\frac{c}{4f\sqrt{{\epsilon }_r}}(f=56GHz\to L_{stub}<0.15mm)$

2. Length & Phase Matching

   • Intra-pair skew: ≤0.05mm (0.3ps @112Gbps)

   • Serpentine Rules:

     • Spacing ≥3×width

     • Bend radius ≥5×width

3. Via Optimization

   Standard Via → UHS Via    Hole: 8mil → 5mil    Pad: 18mil → 12mil    Add: Back-drill +2mil, GND via array (pitch=25mil)  

   Effect: Return loss improved by 15dB@56GHz

IV. Signal Integrity Enhancement

1. Transmitter Equalization (FFE)

   • Optimized 3-tap FFE:
     $[C_{-1},C_0,C_1]=[-0.15,1.0,-0.08](40\mathrm{\%}\text{ eye improvement})$
     

2. Receiver Equalization (CTLE+DFE)

   Type	Gain Compensation	Application
   CTLE	3-8dB @ Nyquist	Mid-range backplane
   DFE	Post-cursor removal	>20" long traces

3. Pre/De-emphasis

   • De-emphasis formula:
     $A_{de}=20\log \left(\frac{1+\beta }{1-\beta }\right)(\beta =0.25\Rightarrow \approx 6\text{dB})$
     

V. Verification & SIMulation Flow

Targets:

• Total loss: < -25dB @56GHz

• Eye height: >25mV @BER=1E-12

• Jitter: <0.15UI

VI. Test Data (112G PAM4 Optical Module)

Validation:

1. VNA: Keysight N5225B (110GHz)

2. BERT: Anritsu MP1900A (PAM4 112Gbps)

3. TDR: Tektronix 70GHz sampling scope