Edge Roughness Control for High-Frequency Circuit (≥25Gbps) Etching to Meet Signal Integrity Requirements

2025-10-14

High-frequency circuits (≥25Gbps) are the backbone of modern high-speed communication systems, including 5G base stations, data center Switches, and advanced test equipment. These circuits rely on precise signal transmission—even minute signal degradation (e.g., attenuation, jitter) can disrupt data integrity, leading to bit error rates (BER) exceeding the industry-acceptable threshold of 10⁻¹².

Among the many factors affecting high-frequency signal integrity, copper circuit edge roughness (Rz/Ra) is often overlooked but critically impactful. When an electromagnetic signal propagates along a high-frequency circuit, the "skin effect" (where current concentrates on the conductor’s suRFace, typically within 1–5μm of the edge at 25Gbps) causes the signal to interact directly with the circuit’s edge. Rough edges create irregular current paths, leading to two key issues:

Signal attenuation: Energy is lost as the current navigates rough edges, increasing insertion loss (IL) by 0.5–2dB/m at 25Gbps.
Signal distortion: Irregular edges introduce impedance discontinuities, which generate reflections and jitter (timing deviation), raising BER to unacceptable levels.

Thus, controlling edge roughness during etching is not just a manufacturing detail—it is a prerequisite for meeting high-frequency signal integrity standards (e.g., IEEE 802.3bs for 25Gbps Ethernet).

2. Key Metrics for Measuring Circuit Edge Roughness

Before defining control thresholds, it is critical to clarify the metrics used to quantify edge roughness, as different standards and applications prioritize different measurements:

Metric	Definition	Relevance to High-Frequency Circuits (≥25Gbps)
Ra (Arithmetic Mean Deviation)	Average of the absolute deviations of roughness profiles from the mean line.	Provides a general measure of smoothness but may underestimate sharp peaks/troughs.
Rz (Ten-Point Mean Roughness)	Average of the five highest peaks and five deepest troughs in a sampling length.	More critical for high frequencies—sharp peaks (common in etched edges) cause severe impedance spikes.
Rmax (Maximum Roughness)	Maximum vertical distance between the highest peak and deepest trough in a sampling length.	Indicates worst-case irregularities; even a single sharp peak can disrupt signal flow.

For circuits ≥25Gbps, Rz and Rmax are the primary control metrics because they capture the extreme edge irregularities that most severely impact signal integrity. Ra is often used as a secondary metric for general quality checks.

3. Edge Roughness Control Thresholds for High-Frequency Circuits (≥25Gbps)

The allowable edge roughness depends on three factors: signal frequency, circuit geometry (line width/spacing), and application-specific signal integrity requirements (e.g., insertion loss limits). Below are industry-validated thresholds, aligned with standards such as IPC-6012DS (high-speed PCB requirements) and IEEE 802.3bs:

3.1 General Threshold for 25–50Gbps Circuits

For most 25–50Gbps applications (e.g., 25G Ethernet, 40G InfiniBand), the following thresholds ensure insertion loss ≤0.8dB/m and jitter ≤0.1UI (unit interval):

Rz ≤ 1.0μm: This is the "golden standard" for 25–50Gbps circuits. Etched edges with Rz >1.0μm introduce impedance variations of ±5Ω (for 50Ω characteristic impedance circuits), exceeding the acceptable ±3Ω range.
Rmax ≤ 1.5μm: Prevents worst-case peaks from causing localized signal reflections. A single peak of 2.0μm can increase BER to 10⁻⁹ (three orders of magnitude above the 10⁻¹² limit).
Ra ≤ 0.2μm: Serves as a secondary check—Ra >0.2μm often indicates widespread roughness that will eventually push Rz above 1.0μm.

Example: A 25Gbps PCB with 50Ω microstrip lines (line width 0.25mm, spacing 0.2mm) must have Rz ≤1.0μm to maintain insertion loss at 0.6dB/m (well within the IEEE 802.3bs limit of 1.0dB/m).

3.2 Strict Threshold for 50–100Gbps Circuits

For higher frequencies (50–100Gbps, e.g., 100G Ethernet, 80G optical transceivers), the skin effect intensifies (current concentrates within 0.5–2μm of the edge), requiring tighter roughness control:

Rz ≤ 0.6μm: Reduces impedance variation to ±2Ω, critical for 50–100Gbps signals that are more sensitive to discontinuities.
Rmax ≤ 1.0μm: Eliminates even minor peaks that could cause jitter >0.05UI.
Ra ≤ 0.15μm: Ensures uniform edge smoothness across the entire circuit length.

Rationale: At 100Gbps, a 0.8μm Rz edge increases insertion loss by 1.2dB/m—surpassing the IEEE 802.3bs limit of 1.0dB/m for 100Gbps links.

3.3 Adjustments for Fine-Pitch Circuits

Fine-pitch circuits (line width/spacing ≤0.15mm, common in high-density 25Gbps+ PCBs) require stricter thresholds because their smaller cross-sectional area amplifies the impact of edge roughness:

Reduce Rz by 20–30%: For 0.1mm line widths (25Gbps), Rz ≤0.8μm (down from 1.0μm for 0.25mm lines).
Rmax ≤1.2μm: Prevents peaks from narrowing the effective line width (e.g., a 1.5μm peak on a 0.1mm line reduces the effective width by 1.5%, causing a 3Ω impedance shift).

4. Etching Process Controls to Achieve Roughness Thresholds

Meeting Rz ≤1.0μm (or stricter) for 25Gbps+ circuits requires optimizing every step of the etching process—conventional etching methods (e.g., spray etching with unoptimized parameters) typically produce Rz =1.5–2.5μm, which is unacceptable for high frequencies. Below are key process controls:

4.1 Etching Chemistry Optimization

Acidic Chloride Etchants: Use low-copper-concentration solutions (Cu²⁺ = 180–200g/L, vs. 220–250g/L for conventional etching). Lower Cu²⁺ reduces "dendritic growth" (sharp copper projections) on edges, cutting Rz by 30–40%.
Additives: Incorporate anti-roughness additives (e.g., benzotriazole derivatives) at 5–10ppm. These additives form a thin film on the copper edge, slowing etching at peaks and reducing Rz to ≤0.8μm.

4.2 Etching Equipment and Parameter Tuning

Low-Pressure Spray Etching: Use spray nozzles with 0.2–0.3mm orifices and reduce pressure to 0.8–1.2kg/cm² (vs. 1.5–2.0kg/cm² for conventional etching). Lower pressure creates a more uniform etch front, minimizing edge irregularities.
Temperature Control: Maintain etchant temperature at 28–30℃ (±1℃). Higher temperatures (＞32℃) accelerate uneven etching, increasing Rz by 0.3–0.5μm.
Etching Time: Adopt "over-etching" of 5–10% (vs. 15–20% for conventional etching). Excessive over-etching causes edge undercutting and roughness; minimal over-etching preserves edge smoothness.

4.3 Post-Etching Surface Treatment

Micro-Etching: Use a mild micro-etchant (e.g., 10% sulfuric acid + hydrogen peroxide) for 10–15 seconds. This removes residual dendritic peaks, reducing Rz by 0.2–0.3μm without damaging the circuit.
Rinse and Dry: Use deionized water (resistivity ≥18MΩ·cm) for rinsing and hot-air drying (50–60℃) to prevent water spots, which can cause localized roughness during storage.

5. Validation and Inspection Methods for Edge Roughness

To confirm that edge roughness meets thresholds, high-frequency PCB manufacturers must implement rigorous inspection protocols:

5.1 Optical Profilometry (Primary Method)

Use a 3D optical profiler (e.g., Keyence VK-X series) with 0.1μm vertical resolution. Sample 5–10 locations per circuit (focusing on high-stress areas like bends and vias), measuring Rz, Rmax, and Ra.
Require 100% inspection for critical 50–100Gbps circuits; use AQL 0.65 sampling for 25–50Gbps circuits (per IPC-A-600H).

5.2 Signal Integrity Testing (Correlative Method)

Measure insertion loss (IL) and return loss (RL) using a vector network analyzer (VNA) with 10MHz–100GHz bandwidth. For 25Gbps circuits:
- IL ≤0.8dB/m confirms Rz ≤1.0μm;
- RL ≥20dB indicates minimal impedance discontinuities (caused by rough edges).
Perform BER testing at the target frequency (e.g., 25Gbps). A BER ≤10⁻¹² validates that edge roughness is not degrading signal quality.

5.3 Cross-Sectional Analysis (Periodic Audit)

Prepare cross-sections of etched circuits (using focused ion beam, FIB) and examine edges under a scanning electron microscope (SEM) at 500–1000x magnification. This reveals hidden edge irregularities (e.g., subsurface roughness) that optical profilers may miss.

6. Conclusion

For high-frequency circuits (≥25Gbps), edge roughness control is a non-negotiable requirement for ensuring signal integrity. The core thresholds are:

25–50Gbps: Rz ≤1.0μm, Rmax ≤1.5μm, Ra ≤0.2μm;
50–100Gbps: Rz ≤0.6μm, Rmax ≤1.0μm, Ra ≤0.15μm;
Fine-pitch circuits: Rz reduced by 20–30% from general thresholds.

Achieving these thresholds requires optimizing etching chemistry (low Cu²⁺ + anti-roughness additives), equipment parameters (low-pressure spray, precise temperature), and post-etching treatment (micro-etching). Validation via optical profometry and signal integrity testing ensures compliance with standards like IPC-6012DS and IEEE 802.3bs.

As signal frequencies continue to rise (e.g., 200Gbps+ in next-generation data centers), edge roughness thresholds will become even tighter (likely Rz ≤0.4μm for 200Gbps). This will drive innovations in etching technologies—such as atomic layer etching (ALE) for atomic-level edge smoothness—cementing edge roughness control as a defining factor in high-speed PCB manufacturing.